Transceivers
Figure 2–4 shows the block diagram of the transmitter PLL.
Figure 2–4. Transmitter PLL
Transmitter PLL
/M(1)
To
Inter-Transceiver Lines
up
Dedicated
/2
Phase
Frequency
Detector
Charge
Pump + Loop
Filter
Voltage
Controlled
Oscillator
REFCLK0
High Speed
Serial Clock
/L(1)
down
Dedicated
INCLK
/2
REFCLK1
Inter-Transceiver Lines[2:0]
Global Clock (2)
Notes to Figure 2–4:
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers (clock multiplication factors).
(2) The global clock line must be driven from an input pin only.
The reference clock input to the transmitter PLL can be derived from:
■
■
■
One of two available dedicated reference clock input pins (REFCLK0
or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
1
Altera® recommends using the dedicated reference clock input
pins (REFCLK0or REFCLK1) to provide reference clock for the
transmitter PLL.
Table 2–2 lists the adjustable parameters in the transmitter PLL.
Table 2–2. Transmitter PLL Specifications
Parameter
Specifications
Input reference frequency range
Data rate support
50 MHz to 622.08 MHz
600 Mbps to 3.125 Gbps
Low, medium, or high
Bandwidth
2–6
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
