Arria GX Architecture
The transmitter PLL output feeds the central clock divider block and the
local clock divider blocks. These clock divider blocks divide the
high-speed serial clock to generate the low-speed parallel clock for the
transceiver PCS logic and PLD-transceiver interface clock.
Transmitter Phase Compensation FIFO Buffer
A transmitter phase compensation FIFO is located at each transmitter
channel’s logic array interface. It compensates for the phase difference
between the transmitter PCS clock and the local PLD clock. The
transmitter phase compensation FIFO is used in all supported functional
modes. The transmitter phase compensation FIFO buffer is eight words
deep in PCI Express (PIPE) mode and four words deep in all other modes.
f
For more details about architecture and clocking, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
Byte Serializer
The byte serializer takes in two-byte wide data from the transmitter phase
compensation FIFO buffer and serializes it into a one-byte wide data at
twice the speed. The transmit data path after the byte serializer is 8 or 10
bits. This allows clocking the PLD-transceiver interface at half the speed
as compared to the transmitter PCS logic. The byte serializer is bypassed
in GIGE mode. After serialization, the byte serializer transmits the least
significant byte (LSByte) first and the most significant byte (MSByte) last.
Figure 2–5 shows byte serializer input and output. datain[15:0]is the
input to the byte serializer from the transmitter phase compensation
FIFO; dataout[7:0]is the output of the byte serializer.
Figure 2–5. Byte Serializer Operation Note (1)
D1
D2
D3
datain[15:0]
{8'h00,8'h01}
{8'h02,8'h03}
xxxx
D1LSByte
D1MSByte
D2LSByte
D2MSByte
xxxxxxxxxx
xxxxxxxxxx
8'h01
8'h00
8'h03
8'h02
dataout[7:0]
Note to Figure 2–5:
(1) datainmay be 16 or 20 bits. dataoutmay be 8 or 10 bits.
Altera Corporation
May 2008
2–7
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
