Arria GX Architecture
Figure 2–3 shows the block diagram of the clock multiplier unit.
Figure 2–3. Clock Multiplier Unit
CMU Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Transmitter Channels [3:2]
Local Clock
TX Clock
Divider Block
Gen Block
Reference Clock
Central Clock
Divider
Transmitter
PLL
from REFCLKs,
Global Clock (1),
Inter-Transceiver
Lines
Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Local Clock
DTiviXderCBlloocckk
Gen Block
Transmitter Channels [1:0]
The transmitter PLL multiplies the input reference clock to generate the
high-speed serial clock required to support the intended protocol. It
implements a half-rate voltage controlled oscillator (VCO) that generates
a clock at half the frequency of the serial data rate for which it is
configured.
Altera Corporation
May 2008
2–5
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
