Arria GX Architecture
Figure 2–2 shows functional blocks that make up a transceiver channel.
Figure 2–2. Arria GX Transceiver Channel Block Diagram
PMA Analog Section
PCS Digital Section
FPGA Fabric
n
Word
Deserializer
Aligner
(1)
m
Phase
Compensation
FIFO Buffer
Rate
Matcher
8B/10B
Decoder
Byte
Deserializer
Clock
Recovery
Unit
(2)
XAUI
Lane
Deskew
Reference
Clock
Receiver
PLL
Transmitter
PLL
Reference
Clock
n
Serializer
m
Phase
Compensation
FIFO Buffer
Byte
Serializer
(1)
8B/10B
Encoder
(2)
Notes to Figure 2–2:
(1) “n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA.
n = 8 or 10.
(2) “m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the
transceiver. m = 8, 10, 16, or 20.
Each transceiver channel is full-duplex and consists of a transmitter
channel and a receiver channel.
The transmitter channel contains the following sub-blocks:
■
■
■
■
■
Transmitter phase compensation first-in first-out (FIFO) buffer
Byte serializer (optional)
8B/10B encoder (optional)
Serializer (parallel-to-serial converter)
Transmitter differential output buffer
The receiver channel contains the following:
■
■
■
■
■
■
■
■
■
■
■
Receiver differential input buffer
Receiver lock detector and run length checker
Clock recovery unit (CRU)
Deserializer
Pattern detector
Word aligner
Lane deskew
Rate matcher (optional)
8B/10B decoder (optional)
Byte deserializer (optional)
Receiver phase compensation FIFO buffer
Altera Corporation
May 2008
2–3
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
