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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Transceivers  
You can configure the transceiver channels to the desired functional  
modes usingthe ALT2GXB MegaCore instance in the Quartus® II  
MegaWizard® Plug-in Manager for the Arria GX device family.  
Depending on the selected functional mode, the Quartus II software  
automatically configures the transceiver channels to employ a subset of  
the sub-blocks listed above.  
Transmitter Path  
This section describes the data path through the Arria GX transmitter. The  
sub-blocks are described in order from the PLD-transmitter parallel  
interface to the serial transmitter buffer.  
Clock Multiplier Unit  
Each transceiver block has a clock multiplier unit (CMU) that takes in a  
reference clock and synthesizes two clocks: a high-speed serial clock to  
serialize the data and a low-speed parallel clock to clock the transmitter  
digital logic (PCS).  
The CMU is further divided into three sub-blocks:  
One transmitter PLL  
One central clock divider block  
Four local clock divider blocks (one per channel)  
2–4  
Arria GX Device Handbook, Volume 1  
Altera Corporation  
May 2008  
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