Transceivers
Serializer (Parallel-to-Serial Converter)
The serializer block clocks in 8- or 10-bit encoded data from the 8B/10B
encoder using the low-speed parallel clock and clocks out serial data
using the high-speed serial clock from the central or local clock divider
blocks. The serializer feeds the data LSB to MSB to the transmitter output
buffer.
Figure 2–7 shows the serializer block diagram.
Figure 2–7. Serializer
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
10
8B/10B
From
Encoder
To Transmitter
Output Buffer
Low-speed parallel clock
High-speed serial clock
CMU
Central /
Local Clock
Divider
Transmitter Buffer
The Arria GX transceiver buffers support the 1.2- and 1.5-V PCML I/O
standard at rates up to 3.125 Gbps. The common mode voltage (VCM) of
the output driver may be set to 600 or 700 mV.
f
Refer to the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
The output buffer, as shown in Figure 2–8, is directly driven by the
high-speed data serializer and consists of a programmable output driver,
a programmable pre-emphasis circuit, and OCT circuitry.
2–10
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
