Transceivers
Figure 2–1 shows a high-level diagram of the transceiver block
architecture divided into four channels.
Figure 2–1. Transceiver Block
Transceiver Block
RX1
Channel 1
TX1
RX0
Channel 0
Arria GX
Logic Array
TX0
Supporting Blocks
(PLLs, State Machines,
Programming)
REFCLK_1
REFCLK_0
RX2
Channel 2
Channel 3
TX2
RX3
TX3
Each transceiver block has:
■
■
■
■
Four transceiver channels with dedicated physical coding sublayer
(PCS) and physical media attachment (PMA) circuitry
One transmitter PLL that takes in a reference clock and generates
high-speed serial clock depending on the functional mode
Four receiver PLLs and clock recovery unit (CRU) to recover clock
and data from the received serial data stream
State machines and other logic to implement special features
required to support each protocol
2–2
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
