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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II and Stratix II GX I/O Standards Support  
Figure 4–10. Differential SSTL-2 Class I Termination  
VTT = 1.25 V  
VTT = 1.25 V  
Differential  
Transmitter  
Differential  
Receiver  
50 Ω  
50 Ω  
25 Ω  
25 Ω  
Z
= 50 Ω  
0
Z
= 50 Ω  
0
Figure 4–11. Differential SSTL-2 Class II Termination  
VTT = 1.25 V  
VTT = 1.25 V  
VTT = 1.25 V  
VTT = 1.25 V  
Differential  
Transmitter  
Differential  
Receiver  
50 Ω  
25 Ω  
50 Ω  
50 Ω  
50 Ω  
Z
= 50 Ω  
= 50 Ω  
0
25 Ω  
Z
0
Differential SSTL-18 Class I and Differential SSTL-18 Class II  
The 1.8-V differential SSTL-18 standard is formulated under JEDEC  
Standard, JESD8-15: Stub Series Terminated Logic for 1.8-V (SSTL_18).  
The differential SSTL-18 I/O standard is a 1.8-V standard used for  
applications such as high-speed DDR2 SDRAM interfaces. This standard  
supports differential signals in systems using the SSTL-18 standard and  
supplements the SSTL-18 standard for differential clocks.  
1
Stratix II and Stratix II GX devices support both input and  
output levels operation.  
4–12  
Stratix II Device Handbook, Volume 2  
Altera Corporation  
January 2008  
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