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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Selectable I/O Standards in Stratix II and Stratix II GX Devices  
Figure 4–5. 1.8-V HSTL Class I Termination  
V
= 0.9 V  
TT  
Output Buffer  
50 Ω  
Input Buffer  
Z = 50 Ω  
V
= 0.9 V  
REF  
Figure 4–6. 1.8-V HSTL Class II Termination  
V
= 0.9 V  
V
= 0.9 V  
TT  
TT  
Output Buffer  
50 Ω  
50 Ω  
Input Buffer  
Z = 50 Ω  
V
= 0.9 V  
REF  
1.5-V HSTL Class I and 1.5-V HSTL Class II  
The 1.5-V HSTL standard is formulated under EIA/JEDEC Standard,  
EIA/JESD8-6: A 1.5-V Output Buffer Supply Voltage Based Interface  
Standard for Digital Integrated Circuits.  
The 1.5-V HSTL I/O standard is used for applications designed to operate  
in the 0.0- to 1.5-V HSTL logic nominal switching range. This standard  
defines single-ended input and output specifications for all  
HSTL-compliant digital integrated circuits. The 1.5-V HSTL I/O standard  
in Stratix II and Stratix II GX devices are compatible with the 1.8-V HSTL  
I/O standard in APEX™ 20KE, APEX 20KC, and in Stratix II and  
Stratix II GX devices themselves because the input and output voltage  
thresholds are compatible (Figures 4–7 and 4–8).  
1
Stratix II and Stratix II GX devices support both input and  
output levels with VREF and VTT.  
Altera Corporation  
January 2008  
4–9  
Stratix II Device Handbook, Volume 2  
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