Selectable I/O Standards in Stratix II and Stratix II GX Devices
f
For detailed information on differential I/O standards, refer to the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II GX Device Handbook.
Differential SSTL-2 Class I and Differential SSTL-2 Class II
The 2.5-V differential SSTL-2 standard is formulated under JEDEC
Standard, JESD8-9A: Stub Series Terminated Logic for 2.5-V (SSTL_2).
This I/O standard is a 2.5-V standard used for applications such as
high-speed DDR SDRAM clock interfaces. This standard supports
differential signals in systems using the SSTL-2 standard and
supplements the SSTL-2 standard for differential clocks. Stratix II and
Stratix II GX devices support both input and output levels. Figures 4–10
and 4–11 shows details on differential SSTL-2 termination.
1
Stratix II and Stratix II GX devices support differential SSTL-2
I/O standards in pseudo-differential mode, which is
implemented by using two SSTL-2 single-ended buffers.
The Quartus® II software only supports pseudo-differential standards on
the INCLK, FBINand EXTCLKports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper VREF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support pseudo-differential
SSTL-2 I/O standards on the left and right I/O banks, you can implement
these standards at these banks. You need to create two pins in the designs
and configure the pins with single-ended SSTL-2 standards. However,
this is limited only to pins that support the differential pin-pair I/O
function and is dependent on the single-ended SSTL-2 standards support
at these banks.
Altera Corporation
January 2008
4–11
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
