Stratix II and Stratix II GX I/O Standards Support
The Quartus II software only supports pseudo-differential standards on
the INCLK, FBINand EXTCLKports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper VREF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support 1.5-V
pseudo-differential HSTL I/O standards on left/right I/O banks, you can
implement these standards at these banks. You need to create two pins in
the designs and configure the pins with single-ended 1.5-V HSTL
standards. However, this is limited only to pins that support the
differential pin-pair I/O function and is dependent on the single-ended
1.8-V HSTL standards support at these banks.
Figure 4–16. 1.5-V Differential HSTL Class I Termination
VTT = 0.75 V
VTT = 0.75 V
Differential
Transmitter
Differential
Receiver
50 Ω
50 Ω
Z
= 50 Ω
= 50 Ω
0
Z
0
4–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
ALTERA [ ALTERA CORPORATION ]
