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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II and Stratix II GX I/O Standards Support  
Figure 4–13. Differential SSTL-18 Class II Termination  
VTT = 0.9 V  
VTT = 0.9 V  
VTT = 0.9 V  
VTT = 0.9 V  
Differential  
Transmitter  
Differential  
Receiver  
50 Ω  
25 Ω  
50 Ω  
50 Ω  
50 Ω  
Z
= 50 Ω  
0
25 Ω  
Z
= 50 Ω  
0
1.8-V Differential HSTL Class I and 1.8-V Differential HSTL Class II  
The 1.8-V differential HSTL specification is the same as the 1.8-V  
single-ended HSTL specification. It is used for applications designed to  
operate in the 0.0- to 1.8-V HSTL logic switching range such as QDR  
memory clock interfaces. Stratix II and Stratix II GX devices support both  
input and output levels operation. Figures 4–14 and 4–15 show details on  
1.8-V differential HSTL termination.  
Stratix II and Stratix II GX devices support 1.8-V differential HSTL I/O  
standards in pseudo-differential mode, which is implemented by using  
two 1.8-V HSTL single-ended buffers.  
The Quartus II software only supports pseudo-differential standards on  
the INCLK, FBINand EXTCLKports of enhanced PLL, as well as on DQS  
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is  
used. Two single-ended output buffers are automatically programmed to  
have opposite polarity so as to implement a pseudo-differential output. A  
proper VREF voltage is required for the two single-ended input buffers to  
implement a pseudo-differential input. In this case, only the positive  
polarity input is used in the speed path while the negative input is not  
connected internally. In other words, only the non-inverted pin is  
required to be specified in your design, while the Quartus II software  
automatically generates the inverted pin for you.  
Although the Quartus II software does not support 1.8-V  
pseudo-differential HSTL I/O standards on left/right I/O banks, you can  
implement these standards at these banks. You need to create two pins in  
the designs and configure the pins with single-ended 1.8-V HSTL  
standards. However, this is limited only to pins that support the  
differential pin-pair I/O function and is dependent on the single-ended  
1.8-V HSTL standards support at these banks.  
4–14  
Stratix II Device Handbook, Volume 2  
Altera Corporation  
January 2008  
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