Stratix II and Stratix II GX I/O Standards Support
Figure 4–7. 1.5-V HSTL Class I Termination
V
= 0.75 V
TT
Output Buffer
50 Ω
Input Buffer
Z = 50 Ω
V
= 0.75 V
REF
Figure 4–8. 1.5-V HSTL Class II Termination
V
= 0.75 V
V
= 0.75 V
TT
TT
Output Buffer
50 Ω
50 Ω
Input Buffer
Z = 50 Ω
V
= 0.75 V
REF
1.2-V HSTL
Although there is no EIA/JEDEC standard available for the 1.2-V HSTL
standard, Altera supports it for applications that operate in the 0.0 to
1.2-V HSTL logic nominal switching range. 1.2-V HSTL can be terminated
through series or parallel on-chip termination (OCT). Figure 4–9 shows
the termination scheme.
Figure 4–9. 1.2-V HSTL Termination
Output Buffer
Input Buffer
Z = 50 Ω
OCT
V
= 0.6 V
REF
Differential I/O Standards
Differential I/O standards are used to achieve even faster data rates with
higher noise immunity. Apart from LVDS, LVPECL, and HyperTransport
technology, Stratix II and Stratix II GX devices also support differential
versions of SSTL and HSTL standards.
4–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
ALTERA [ ALTERA CORPORATION ]
