Stratix II and Stratix II GX I/O Standards Support
1
Stratix II and Stratix II GX devices support both input and
output levels operation.
Figure 4–3. 1.8-V SSTL Class I Termination
V
= 0.9 V
TT
Output Buffer
25 Ω
50 Ω
Input Buffer
Z = 50 Ω
V
= 0.9 V
REF
Figure 4–4. 1.8-V SSTL Class II Termination
V
= 0.9 V
V
= 0.9 V
TT
TT
Output Buffer
50 Ω
50 Ω
Input Buffer
Z = 50 Ω
25 Ω
V
= 0.9 V
REF
1.8-V HSTL Class I and 1.8-V HSTL Class II
The HSTL standard is a technology-independent I/O standard
developed by JEDEC to provide voltage scalability. It is used for
applications designed to operate in the 0.0- to 1.8-V HSTL logic switching
range such as quad data rate (QDR) memory clock interfaces.
Although JEDEC specifies a maximum VCCIO value of 1.6 V, there are
various memory chip vendors with HSTL standards that require a VCCIO
of 1.8 V. Stratix II and Stratix II GX devices support interfaces to chips
with VCCIO of 1.8 V for HSTL. Figures 4–5 and 4–6 show the nominal VREF
and VTT required to track the higher value of VCCIO. The value of VREF is
selected to provide optimum noise margin in the system.
1
Stratix II and Stratix II GX devices support both input and
output levels operation.
4–8
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
ALTERA [ ALTERA CORPORATION ]
