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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II and Stratix II GX I/O Standards Support  
The PCI local bus specification is used for applications that interface to  
the PCI local bus, which provides a processor-independent data path  
between highly integrated peripheral controller components, peripheral  
add-in boards, and processor/memory systems. The conventional PCI  
specification revision 2.2 defines the PCI hardware environment  
including the protocol, electrical, mechanical, and configuration  
specifications for the PCI devices and expansion boards. This standard  
requires 3.3-V VCCIO. Stratix II and Stratix II GX devices are fully  
compliant with the 3.3-V PCI Local Bus Specification Revision 2.2 and  
meet 64-bit/66-MHz operating frequency and timing requirements.  
1
The 3.3-V PCI standard does not require input reference  
voltages or board terminations. Stratix II and Stratix II GX  
devices support both input and output levels.  
3.3-V PCI-X  
The 3.3-V PCI-X I/O standard is formulated under PCI-X Local Bus  
Specification Revision 1.0a developed by the PCI SIG.  
The PCI-X 1.0 standard is used for applications that interface to the PCI  
local bus. The standard enables the design of systems and devices that  
operate at clock speeds up to 133 MHz, or 1 Gbps for a 64-bit bus. The  
PCI-X 1.0 protocol enhancements enable devices to operate much more  
efficiently, providing more usable bandwidth at any clock frequency. By  
using the PCI-X 1.0 standard, you can design devices to meet PCI-X 1.0  
requirements and operate as conventional 33- and 66-MHz PCI devices  
when installed in those systems. This standard requires 3.3-V VCCIO  
.
Stratix II and Stratix II GX devices are fully compliant with the 3.3-V  
PCI-X Specification Revision 1.0a and meet the 133-MHz operating  
frequency and timing requirements. The 3.3-V PCI-X standard does not  
require input reference voltages or board terminations.  
1
Stratix II and Stratix II GX devices support both input and  
output levels operation.  
SSTL-2 Class I and SSTL-2 Class II  
The 2.5-V SSTL-2 standard is formulated under JEDEC Standard,  
JESD8-9A: Stub Series Terminated Logic for 2.5-V (SSTL_2).  
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for  
applications such as high-speed DDR SDRAM interfaces. This standard  
defines the input and output specifications for devices that operate in the  
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves  
4–6  
Stratix II Device Handbook, Volume 2  
Altera Corporation  
January 2008  
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