Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–1. Stratix II and Stratix II GX I/O Standard Applications (Part 2 of 2)
I/O Standard
Application
1.5-V differential HSTL Class II
LVDS
Clock interfaces
High-speed communications
PCB interfaces
HyperTransport™ technology
Differential LVPECL
Video graphics and clock distribution
Single-Ended I/O Standards
In non-voltage-referenced single-ended I/O standards, the voltage at the
input must be above a set voltage to be considered “on” (high, or logic
value 1) or below another voltage to be considered “off” (low, or logic
value 0). Voltages between the limits are undefined logically, and may fall
into either a logic value 0 or 1. The non-voltage-referenced single-ended
I/O standards supported by Stratix II and Stratix II GX devices are:
■
■
■
■
■
■
■
Low-voltage transistor-transistor logic (LVTTL)
Low-voltage complementary metal-oxide semiconductor (LVCMOS)
1.5 V
1.8 V
2.5 V
3.3-V PCI
3.3-V PCI-X
Voltage-referenced, single-ended I/O standards provide faster data rates.
These standards use a constant reference voltage at the input levels. The
incoming signals are compared with this constant voltage and the
difference between the two defines “on” and “off” states.
1
Stratix II and Stratix II GX devices support stub series
terminated logic (SSTL) and high-speed transceiver logic
(HSTL) voltage-referenced I/O standards.
LVTTL
The LVTTL standard is formulated under EIA/JEDEC Standard, JESD8-B
(Revision of JESD8-A): Interface Standard for Nominal 3-V/3.3-V Supply
Digital Integrated Circuits.
The standard defines DC interface parameters for digital circuits
operating from a 3.0- or 3.3-V power supply and driving or being driven
by LVTTL-compatible devices. The 3.3-V LVTTL standard is a
Altera Corporation
January 2008
4–3
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
