External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–17. DQ Captures with Non-Inverted and Inverted Shifted DQS
DQ & DQS Signals
DQ at the pin
D
D
n
n − 1
DQS at the pin
Shifted DQS Signal is Not Inverted
DQS shifted
by 90˚
Output of register A
1
D
n − 1
(dataout_h)
D
D
n
Output of register B
1
n − 2
Output of latch C
1
D
n − 2
(dataout_l)
Shifted DQS Signal is Inverted
DQS inverted and
shifted by 90˚
Output of register A
1
D
D
n
n − 2
(dataout_h)
D
Output of register B
1
n − 1
Output of latch C
1
D
D
n − 1
n − 3
(dataout_l)
Altera Corporation
January 2008
3–37
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
