External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–16. DQS Configuration in Stratix II or Stratix II GX IOE
Note (1)
DFF
OE
(2)
D
Q
OE Register A
OE
OR2
1
0
(3)
DFF
D
Q
OE Register B
OE
DFF
Logic Array
D
Q
datain_h (4)
DQS Pin (5)
TRI
1
0
Output Register A
O
DFF
D
Q
datain_l (4)
Output Register B
O
system clock
combout (7)
Notes to Figure 3–16:
(1) You can use the altdqsmegafunction to generate the DQS signals. You should, however, use Altera’s memory
controller IP Tool Bench to generate the data path for your memory interface. The signal names used here match
with Quartus II software naming convention.
(2) The OEsignal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before OEregister AOE during compilation. In RLDRAM II and QDRII SRAM, the OEsignal is always
disabled.
(3) The select line can be chosen in the altdqsmegafunction.
(4) The datain_land datain_hpins are usually connected to ground and VCC, respectively.
(5) DQS postamble circuitry and handling is not shown in this diagram. For more information, see AN 327: Interfacing
DDR SDRAM with Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II Devices.
(6) DQS logic blocks are only available with DQS and DQSn pins.
(7) You must invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the altdq
megafunction to generate the DQ signals. Connect this port to the inclockport in the altdqmegafunction.
Altera Corporation
January 2008
3–35
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
