Clocking
Table 1–24. Stratix II GX Global and Regional Clock Outputs From PLLs (Part 3 of 3)
PLL Number and Type
EP2SGX60 through EP2SGX130 Devices
Notes (2), (3), and (4)
EP2SGX30 Devices
Fast PLLs
Clock Network
Enhanced
PLLs
Enhanced
PLLs
Fast PLLs
1
2
3 (1) 4 (1)
5
6
7
8
9 (1) 10(1) 11
12
v
v
v
v
v
RCLK28
v
v
v
RCLK29
RCLK30
RCLK31
External Clock Output
v
PLL5_OUT[3..0]p
/n
v
PLL6_OUT[3..0]p
/n
v
PLL11_OUT[3..0]
p/n
v
PLL12_OUT[3..0]
p/n
Notes to Table 1–24:
(1) PLLs 3, 4, 9, and 10 are not available in Stratix II GX devices.
(2) The EP2S60 device in the 1,020-pin package contains 12 PLLs. EP2S60 devices in the 484-pin and 672-pin packages
contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
(3) EP2S90 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. EP2S90 devices in the 484-pin and 780-pin
packages contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
(4) EP2S130 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. The EP2S130 device in the 780-pin
package contains fast PLLs 1–4 and enhanced PLLs 5 and 6.
The fast PLLs also drive high-speed SERDES clocks for differential I/O
interfacing. For information about these FPLLCLKpins, contact Altera
Applications.
1–82
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
