Clock Control Block
Figure 1–51. Stratix II GX Corner Fast PLLs, Clock Pin and Logic Array Signal
Connectivity to Global and Regional Clock Networks Note (1)
RCK1
RCK3
RCK0
RCK2
C0
C1
C2
C3
Fast
PLL 7
FPLL7CLK
C0
C1
C2
C3
Fast
PLL 8
FPLL8CLK
RCK4
RCK6
GCK0
GCK2
RCK5
RCK7
GCK1
GCK3
Note to Figure 1–51:
(1) The corner FPLLs can also be driven through the global or regional clock networks.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
Each global and regional clock has its own clock control block. The
control block has two functions:
Clock Control
Block
■
■
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable or disable)
1–86
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
