PLLs in Stratix II and Stratix II GX Devices
Table 1–23. Stratix II Global and Regional Clock Outputs From PLLs (Part 2 of 3)
PLL Number and Type
EP2S15 through EP2S30 Devices EP2S60 through EP2S180 Devices
Clock Network
Enhanced
PLLs
Enhanced
PLLs
Fast PLLs
Fast PLLs
1
2
3
4
5
6
7
8
9
10
11
12
v
v
v
v
v
v
v
v
v
v
v
v
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
RCLK16
RCLK17
RCLK18
RCLK19
RCLK20
RCLK21
RCLK22
RCLK23
RCLK24
RCLK25
RCLK26
RCLK27
RCLK28
RCLK29
RCLK30
RCLK31
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
External Clock Output
v
PLL5_OUT[3..0]p/
n
v
PLL6_OUT[3..0]p/
n
Altera Corporation
July 2009
1–79
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
