Clocking
Figure 1–49. Stratix II GX Center Fast PLLs, Clock Pin and Logic Array Signal Connectivity to Global and
Regional Clock Networks
Notes (1) and (2)
C0
C1
C2
C3
CLK0
Fast
PLL 1
CLK1
Logic Array
Signal Input
To Clock
Network
C0
C1
C2
C3
Fast
PLL 2
CLK2
CLK3
RCK0
RCK2
RCK4
RCK6
GCK0
GCK2
RCK1
RCK3
RCK5
RCK7
GCK1
GCK3
Notes to Figure 1–49:
(1) The redundant connection dots facilitate stitching of the clock networks to support the ability to drive two
quadrants with the same clock.
(2) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. The global or regional clock input
can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
global or regional clock. An internally generated global signal cannot drive the PLL.
1–84
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
