Clocking
Tables 1–23 and 1–24 show the global and regional clocks that the PLL
outputs drive.
Table 1–23. Stratix II Global and Regional Clock Outputs From PLLs (Part 1 of 3)
PLL Number and Type
EP2S15 through EP2S30 Devices
Enhanced
EP2S60 through EP2S180 Devices
Clock Network
Enhanced
PLLs
Fast PLLs
Fast PLLs
PLLs
1
2
3
4
5
6
7
8
9
10
11
12
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
GCLK13
GCLK14
GCLK15
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
RCLK9
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
1–78
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
