Clocking
Table 1–23. Stratix II Global and Regional Clock Outputs From PLLs (Part 3 of 3)
PLL Number and Type
EP2S15 through EP2S30 Devices
EP2S60 through EP2S180 Devices
Clock Network
Enhanced
PLLs
Enhanced
PLLs
Fast PLLs
Fast PLLs
1
2
3
4
5
6
7
8
9
10
11
12
v
PLL11_OUT[3..0]p
/n
v
PLL12_OUT[3..0]p
/n
Table 1–24. Stratix II GX Global and Regional Clock Outputs From PLLs (Part 1 of 3)
PLL Number and Type
EP2SGX60 through EP2SGX130 Devices
EP2SGX30 Devices
Fast PLLs
Notes (2), (3), and (4)
Clock Network
Enhanced
PLLs
Enhanced
Fast PLLs
PLLs
1
2
3 (1) 4 (1)
5
6
7
8
9 (1) 10(1) 11
12
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
GCLK13
GCLK14
GCLK15
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
1–80
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
