PLLs in Stratix II and Stratix II GX Devices
Table 1–4. Enhanced PLL Input Signals (Part 2 of 2)
Port Description
areset
Source
Destination
Signal used to reset the PLL which Logic array
resynchronizes all the counter
General PLL control
signal
outputs. Active high.
Enables the outputs from the phase Logic array
frequency detector. Active high.
PFD
pfdena
Serial clock signal for the real-time
PLL reconfiguration feature.
Logic array
Reconfiguration circuit
Reconfiguration circuit
Reconfiguration circuit
Reconfiguration circuit
scanclk
scandata
scanwrite
scanread
Serial input data stream for the real- Logic array
time PLL reconfiguration feature.
Enables writing the data in the scan Logic array
chain into the PLL. Active high.
Enables scan data to be written into Logic array
the scan chain. Active high.
Table 1–5. Enhanced PLL Output Signals (Part 1 of 2)
Port Description
c[5..0]
Source
Destination
PLL output counters driving regional, PLL counter
global or external clocks.
Internal or external clock
These are three differential or six
single-ended external clock output
pins fed from the C[5..0]PLL
counters, and every output can be
driven by any counter. p and n are
the positive (p) and negative (n) pins
for differential pins.
PLL counter
Pin(s)
pll_out [2..0]p
pll_out [2..0]n
Signal indicating the switch-over
circuit detected a switch-over
condition.
PLL switch-over
circuit
Logic array
Logic array
clkloss
Signals indicating which reference
clock is no longer toggling.
PLL switch-over
circuit
clkbad[1..0]
clkbad1indicates inclk1
status, clkbad0indicates
inclk0status. 1= good; 0=bad
Lock or gated lock output from lock PLL lock detect
detect circuit. Active high.
Logic array
Logic array
locked
Signal to indicate which clock
PLL clock
activeclock
(0=inclk0or 1 =inclk1) is
driving the PLL. If this signal is low,
inclk0drives the PLL, If this signal
is high, inclk1drives the PLL
multiplexer
Altera Corporation
July 2009
1–11
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
