PLLs in Stratix II and Stratix II GX Devices
Figure 1–5. External Clock Output Connectivity to PLL Output Counters for Enhanced PLLs 5, 6, 11 and 12
Note (1)
C0
C1
6
6
To I/O pins (1)
C3
6
From internal logic
or IOE
C4
C5
C6
Multiplexer Selection
Set in Configuration File
Note to Figure 1–5:
(1) The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins
are multiplexed with I/O element (IOE) outputs.
Each pin of a single-ended output pair can either be in phase or 180° out
of phase. The Quartus II software places the NOTgate in the design into
the IOE to implement 180° phase with respect to the other pin in the pair.
The clock output pin pairs support the same I/O standards as standard
output pins (in the top and bottom banks) as well as LVDS, LVPECL,
differential HSTL, and differential SSTL. See Table 1–6, in the “Enhanced
PLL Pins” section on page 1–12 to determine which I/O standards the
enhanced PLL clock pins support.
When in single-ended or differential mode, one power pin supports six
single-ended or three differential outputs. Both outputs use the same I/O
standard in single-ended mode to maintain performance. You can also
use the external clock output pins as user output pins if external
enhanced PLL clocking is not needed.
The enhanced PLL can also drive out to any regular I/O pin through the
global or regional clock network.
Enhanced PLL Software Overview
Stratix II and Stratix II GX enhanced PLLs are enabled in the Quartus II
software by using the altpllmegafunction. Figure 1–6 shows the
available ports (as they are named in the Quartus II altpll
megafunction) of the Stratix II and Stratix II GX enhanced PLL.
Altera Corporation
July 2009
1–9
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
