Enhanced PLLs
Table 1–7. Stratix II and Stratix II GX Enhanced PLL Pins (Part 2 of 3)
Note (1)
Pin
PLL6_FBp/n
Description
Single-ended or differential pins that can drive the fbinport for PLL 6.
Single-ended or differential pins that can drive the fbinport for PLL 11.
Single-ended or differential pins that can drive the fbinport for PLL 12.
PLL11_FBp/n
PLL12_FBp/n
PLL_ENA
Dedicated input pin that drives the pllenaport of all or a set of PLLs. If you do
not use this pin, connect it to ground.
PLL5_OUT[2..0]p/n
PLL6_OUT[2..0]p/n
PLL11_OUT[2..0]p/n
PLL12_OUT[2..0]p/n
VCCA_PLL5
Single-ended or differential pins driven by C[5..0]ports from PLL 5.
Single-ended or differential pins driven by C[5..0]ports from PLL 6.
Single-ended or differential pins driven by C[5..0]ports from PLL 11.
Single-ended or differential pins driven by C[5..0]ports from PLL 12.
Analog power for PLL 5. You must connect this pin to 1.2 V, even if the PLL is not
used.
Analog ground for PLL 5. You can connect this pin to the GND plane on the board.
GNDA_PLL5
VCCA_PLL6
Analog power for PLL 6. You must connect this pin to 1.2 V, even if the PLL is not
used.
Analog ground for PLL 6. You can connect this pin to the GND plane on the board.
GNDA_PLL6
Analog power for PLL 11. You must connect this pin to 1.2 V, even if the PLL is not
used.
VCCA_PLL11
Analog ground for PLL 11. You can connect this pin to the GND plane on the
board.
GNDA_PLL11
VCCA_PLL12
GNDA_PLL12
VCCD_PLL
Analog power for PLL 12. You must connect this pin to 1.2 V, even if the PLL is not
used.
Analog ground for PLL 12. You can connect this pin to the GND plane on the
board.
Digital power for PLLs. You must connect this pin to 1.2 V, even if the PLL is not
used.
VCC_PLL5_OUT
External clock output VCCIO power for PLL5_OUT0p, PLL5_OUT0n,
PLL5_OUT1p, PLL5_OUT1n, PLL5_OUT2p, and PLL5_OUT2noutputs from
PLL 5.
VCC_PLL6_OUT
VCC_PLL11_OUT
External clock output VCCIO power for PLL6_OUT0p, PLL6_OUT0n,
PLL6_OUT1p, PLL6_OUT1nand PLL6_OUT2p, PLL6_OUT2noutputs from
PLL 6.
External clock output VCCIO power for PLL11_OUT0p, PLL11_OUT0n,
PLL11_OUT1p, PLL11_OUT1nand PLL11_OUT2p, PLL11_OUT2noutputs
from PLL 11.
1–14
Altera Corporation
Stratix II Device Handbook, Volume 2
July 2009
ALTERA [ ALTERA CORPORATION ]
