Enhanced PLLs
Figure 1–6. Enhanced PLL Ports
Physical Pin
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
(1)
(2), (3)
(2), (3)
pllena
inclk0
inclk1
(4)
C[5..0]
locked
clkloss
activeclock
scandataout
scanclk
scanwrite
scanread
scandata
clkbad[1..0]
scandone
fbin
clkswitch
areset
pfdena
(5)
(5)
pll_out0p
pll_out0n
(5)
(5)
pll_out1p
pll_out1n
(5)
(5)
pll_out2p
pll_out2n
Notes to Figure 1–6:
(1) Enhanced and fast PLLs share this input pin.
(2) These are either single-ended or differential pins.
(3) The primary and secondary clock input can be fed from any one of four clock pins located on the same side of the
device as the PLL.
(4) Can drive to the global or regional clock networks or the dedicated external clock output pins.
(5) These dedicated output clocks are fed by the C[5..0]counters.
Tables 1–4 and 1–5 describe all the enhanced PLL ports.
Table 1–4. Enhanced PLL Input Signals (Part 1 of 2)
Port
inclk0
Description
Source
Destination
Primary clock input to the PLL.
Secondary clock input to the PLL.
Pin or another PLL
Pin or another PLL
n counter
n counter
inclk1
fbin
External feedback input to the PLL. Pin
PFD
Enable pin for enabling or disabling Pin
all or a set of PLLs. Active high.
General PLL control
signal
pllena
Switch-over signal used to initiate
external clock switch-over control.
Active high.
Logic array
PLL switch-over circuit
clkswitch
1–10
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
