PLLs in Stratix II and Stratix II GX Devices
Figure 1–3. Stratix II and Stratix II GX Enhanced PLL
From Adjacent PLL
VCO Phase Selection
Selectable at Each
PLL Output Port
Post-Scale
Counters
Clock
Switchover
Circuitry
Spread
Spectrum
÷c0
÷c1
Phase Frequency
Detector
INCLK[3..0]
4
4
8
6
Global
Clocks
÷n
8
Charge
Pump
Loop
Filter
÷c2
PFD
VCO
6
Regional
Clocks
Global or
Regional
Clock
÷c3
÷c4
÷c5
I/O Buffers
(2)
÷m
(1)
to I/O or general
routing
Lock Detect
& Filter
FBIN
Shaded Portions of the
PLL are Reconfigurable
VCO Phase Selection
Affecting All Outputs
Notes to Figure 1–3:
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) PLLs 5, 6, 11, and 12 each have six single-ended dedicated clock outputs or three differential dedicated clock
outputs.
(3) If the design uses external feedback input pins, you will lose one (or two, if fBIN is differential) dedicated output
clock pin. Every Stratix II and Stratix II GX device has at least two enhanced PLLs with one single-ended or
differential external feedback input per PLL.
(4) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
Altera Corporation
July 2009
1–7
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
