Enhanced PLLs
Table 1–5. Enhanced PLL Output Signals (Part 2 of 2)
Port
Description
Source
Destination
Output of the last shift register in the PLL scan chain
scan chain.
Logic array
scandataout
Signal indicating when the PLL has PLL scan chain
completed reconfiguration. 1 to 0
transition indicates that the PLL has
been reconfigured.
Logic array
scandone
Enhanced PLL Pins
Table 1–6 lists the I/O standards support by the enhanced PLL clock
outputs.
Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2)
Note (1)
Input
Output
I/O Standard
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
FBIN
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
EXTCLK
v
LVTTL
LVCMOS
2.5 V
v
v
1.8 V
v
1.5 V
v
3.3-V PCI
3.3-V PCI-X
v
v
SSTL-2 Class I
v
SSTL-2 Class II
v
SSTL-18 Class I
v
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL Class I
1.2-V HSTL Class II
v
v
v
v
v
v
v
1–12
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
