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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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PLLs in Stratix II and Stratix II GX Devices  
Table 1–7. Stratix II and Stratix II GX Enhanced PLL Pins (Part 3 of 3)  
Note (1)  
Pin  
Description  
VCC_PLL12_OUT  
External clock output VCCIO power for PLL12_OUT0p, PLL12_OUT0n,  
PLL12_OUT1p, PLL12_OUT1nand PLL12_OUT2p, PLL12_OUT2noutputs  
from PLL 12.  
Note to Table 1–7:  
(1) The negative leg pins (CLKn, PLL_FBn, and PLL_OUTn) are only required with differential signaling.  
Stratix II devices contain up to eight fast PLLs and Stratix II GX devices  
contain up to four fast PLLs. Fast PLLs have high-speed differential I/O  
interface capability along with general-purpose features.  
Fast PLLs  
Fast PLL Hardware Overview  
Figure 1–7 shows a diagram of the fast PLL.  
Figure 1–7. Stratix II and Stratix II GX Fast PLL Block Diagram  
Post-Scale  
Counters  
VCO Phase Selection  
Selectable at each PLL  
Output Port  
Clock (1)  
Switchover  
Circuitry  
Phase  
Frequency  
Detector  
diffioclk0 (3)  
loaden0 (4)  
Global or  
regional clock (2)  
÷c0  
÷c1  
÷c2  
diffioclk1 (3)  
loaden1 (4)  
(5)  
8
Charge  
Pump  
Loop  
Filter  
÷k  
÷n  
PFD  
VCO  
4
Clock  
Input  
4
8
Global clocks  
4
Global or  
regional clock (2)  
Regional clocks  
÷c3  
÷m  
8
Shaded Portions of the  
PLL are Reconfigurable  
to DPA block  
Notes to Figure 1–7:  
(1) Stratix II and Stratix II GX fast PLLs only support manual clock switchover.  
(2) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or  
regional clock, or through a clock control block provided the clock control block is fed by an output from another  
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.  
(3) In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix II devices only  
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.  
(4) This signal is a high-speed differential I/O support SERDES control signal.  
(5) If the design enables this ÷2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.  
Altera Corporation  
July 2009  
1–15  
Stratix II Device Handbook, Volume 2  
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