Enhanced PLLs
The PFD output is applied to the charge pump and loop filter, which
produces a control voltage for setting the VCO frequency. If the PFD
produces an up signal, then the VCO frequency increases. A down signal
decreases the VCO frequency. The PFD outputs these up and down
signals to a charge pump. If the charge pump receives an up signal,
current is driven into the loop filter. Conversely, if it receives a down
signal, current is drawn from the loop filter.
The loop filter converts these up and down signals to a voltage that is
used to bias the VCO. The loop filter also removes glitches from the
charge pump and prevents voltage over-shoot, which filters the jitter on
the VCO.
The voltage from the loop filter determines how fast the VCO operates.
The VCO is implemented as a four-stage differential ring oscillator. A
divide counter (m) is inserted in the feedback loop to increase the VCO
frequency above the input reference frequency. VCO frequency (fVCO) is
equal to (m) times the input reference clock (fREF). The input reference
clock (fREF) to the PFD is equal to the input clock (fIN) divided by the pre-
scale counter (n). Therefore, the feedback clock (fFB) applied to one input
of the PFD is locked to the fREF that is applied to the other input of the
PFD.
The VCO output can feed up to six post-scale counters (C0, C1, C2, C3, C4,
and C5). These post-scale counters allow a number of harmonically
related frequencies to be produced within the PLL.
Figure 1–3 shows a simplified block diagram of the major components of
the Stratix II and Stratix II GX enhanced PLL. Figure 1–4 shows the
enhanced PLL’s outputs and dedicated clock outputs.
1–6
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
ALTERA [ ALTERA CORPORATION ]
