PLLs in Stratix II and Stratix II GX Devices
Figure 1–2. Stratix II GX PLL Locations
CLK[15..12]
11 5
7
FPLL7CLK
1
2
CLK[3..0]
PLLs
FPLL8CLK
8
12
6
CLK[7..4]
Stratix II and Stratix II GX devices contain up to four enhanced PLLs with
advanced clock management features. The main goal of a PLL is to
synchronize the phase and frequency of an internal and external clock to
an input reference clock. There are a number of components that
comprise a PLL to achieve this phase alignment.
Enhanced PLLs
Enhanced PLL Hardware Overview
Stratix II and Stratix II GX PLLs align the rising edge of the reference
input clock to a feedback clock using the phase-frequency detector (PFD).
The falling edges are determined by the duty-cycle specifications. The
PFD produces an up or down signal that determines whether the VCO
needs to operate at a higher or lower frequency.
Altera Corporation
July 2009
1–5
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
