Stratix II Architecture
Table 2–19. Board Design Recommendations for nCEO
Stratix II nCEO VCCIO Voltage Level in I/O Bank 7
nCE Input Buffer Power in I/O
Bank 3
VCCIO
3.3 V
=
VCCIO
=
VCCIO
=
VCCIO
=
VCCIO
=
2.5 V
1.8 V
1.5 V
1.2 V
VCCSELhigh
(VCCIO Bank 3 = 1.5 V)
v(1), (2)
v(1), (2)
v
v(3), (4)
v(3), (4)
v(4)
v(5)
v
v
v
v
Level shifter
required
VCCSELhigh
(VCCIO Bank 3 = 1.8 V)
Level shifter Level shifter
required required
VCCSELlow
(nCE Powered by VCCPD = 3.3V)
v(6)
Notes to Table 2–19:
(1) Input buffer is 3.3-V tolerant.
(2) The nCEOoutput buffer meets VO H (MIN) = 2.4 V.
(3) Input buffer is 2.5-V tolerant.
(4) The nCEOoutput buffer meets VOH (MIN) = 2.0 V.
(5) Input buffer is 1.8-V tolerant.
(6) An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
For JTAG chains, the TDOpin of the first device drives the TDIpin of the
second device in the chain. The VCCSEL input on JTAG input I/O cells
(TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting the
3.3-V/2.5-V input buffer powered by VCCPD. The ideal case is to have the
VCCIO of the TDObank from the first device to match the VCCSEL settings
for TDIon the second device, but that may not be possible depending on
the application. Table 2–20 contains board design recommendations to
ensure proper JTAG chain operation.
Table 2–20. Supported TDO/TDI Voltage Combinations (Part 1 of 2)
Stratix II TDO VCCIO Voltage Level in I/O Bank 4
TDI Input
Device
Buffer Power
VCCI O = 3.3 V VCCIO = 2.5 V VCCIO = 1.8 V VCCIO = 1.5 V VCCI O = 1.2 V
Stratix II
Always
VCCPD (3.3V)
Level shifter
required
Level shifter
required
v(1)
v(2)
v(3)
Altera Corporation
May 2007
2–95
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
