I/O Structure
Table 2–18 summarizes Stratix II MultiVolt I/O support.
Table 2–18. Stratix II MultiVolt I/O Support Note (1)
Input Signal (V)
VCCIO (V)
Output Signal (V)
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3 5.0
1.2
1.5
1.8
2.5
3.3
(4)
(4)
(4)
(4)
(4)
v (2)
v
v
v (2)
v
v
v(2)
v(2)
v(2)
v
v(2)
v(2)
v(2)
v
v (4)
v (3)
v
v(3) v(3)
v
v(3) v(3) v(3)
v(3) v(3) v(3)
v
v(3)
v
v
v
v
Notes to Table 2–18:
(1) To drive inputs higher than VCCIO but less than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL
and LVCMOS input levels to overdrive input buffer option in the Quartus II software.
(2) The pin current may be slightly higher than the default value. You must verify that the driving device’s VOL
maximum and VO H minimum voltages do not violate the applicable Stratix II VIL maximum and VIH minimum
voltage specifications.
(3) Although VCCIO specifies the voltage necessary for the Stratix II device to drive out, a receiving device powered at
a different level can still interface with the Stratix II device if it has inputs that tolerate the VCCIO value.
(4) Stratix II devices do not support 1.2-V LVTTL and 1.2-V LVCMOS. Stratix II devices support 1.2-V HSTL.
The TDOand nCEOpins are powered by VCCIO of the bank that they reside
in. TDOis in I/O bank 4 and nCEOis in I/O bank 7.
Ideally, the VCC supplies for the I/O buffers of any two connected pins are
at the same voltage level. This may not always be possible depending on
the VCCIO level of TDOand nCEOpins on master devices and the
configuration voltage level chosen by VCCSELon slave devices. Master
and slave devices can be in any position in the chain. Master indicates that
it is driving out TDOor nCEOto a slave device.
For multi-device passive configuration schemes, the nCEOpin of the
master device drives the nCEpin of the slave device. The VCCSELpin on
the slave device selects which input buffer is used for nCE. When VCCSEL
is logic high, it selects the 1.8-V/1.5-V buffer powered by VCCIO. When
VCCSELis logic low it selects the 3.3-V/2.5-V input buffer powered by
VCCPD. The ideal case is to have the VCCIO of the nCEObank in a master
device match the VCCSELsettings for the nCEinput buffer of the slave
device it is connected to, but that may not be possible depending on the
application. Table 2–19 contains board design recommendations to
ensure that nCEOcan successfully drive nCEfor all power supply
combinations.
2–94
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
