Stratix II Architecture
device, PLL 1 can drive a maximum of 10 transmitter channels in I/O
bank 1 or a maximum of 19 transmitter channels in I/O banks 1 and 2. The
Quartus II software may also merge receiver and transmitter PLLs when
a receiver is driving a transmitter. In this case, one fast PLL can drive both
the maximum numbers of receiver and transmitter channels.
Table 2–21. EP2S15 Device Differential Channels
Note (1)
Center Fast PLLs
Transmitter/
Receiver
Total
Channels
Package
PLL 1
PLL 2
PLL 3
PLL 4
484-pin FineLine BGA
Transmitter
38 (2)
(3)
10
19
11
21
10
19
11
21
9
9
10
19
11
21
10
19
11
21
19
10
21
9
19
10
21
9
Receiver
42 (2)
(3)
672-pin FineLine BGA
Transmitter
Receiver
38 (2)
(3)
19
10
21
19
10
21
42 (2)
(3)
Table 2–22. EP2S30 Device Differential Channels
Note (1)
Center Fast PLLs
Transmitter/
Receiver
Total
Channels
Package
PLL 1
PLL 2
PLL 3
PLL 4
484-pin FineLine BGA
Transmitter
38 (2)
(3)
10
19
11
21
16
29
17
31
9
9
10
19
11
21
16
29
17
31
19
10
21
13
29
14
31
19
10
21
13
29
14
31
Receiver
42 (2)
(3)
672-pin FineLine BGA
Transmitter
Receiver
58 (2)
(3)
62 (2)
(3)
Altera Corporation
May 2007
2–97
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
