Stratix II Architecture
Table 2–25. EP2S130 Differential Channels
Note (1)
Center Fast PLLs
Corner Fast PLLs (4)
Transmitter/
Receiver Channels
Total
Package
PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10
780-pin
FineLine BGA
Transmitter
Receiver
64 (2)
(3)
16
32
17
34
22
44
23
46
37
78
37
78
16
32
17
34
22
44
23
46
41
78
41
78
16
32
17
34
22
44
23
46
41
78
41
78
16
32
17
34
22
44
23
46
37
78
37
78
-
-
-
-
-
-
-
-
68 (2)
(3)
-
-
-
-
-
-
1,020-pin
FineLine BGA
Transmitter
Receiver
88 (2)
(3)
22
-
22
-
22
-
22
-
92 (2)
(3)
23
-
23
-
23
-
23
-
1,508-pin
FineLine BGA
Transmitter
Receiver
156 (2)
(3)
37
-
41
-
41
-
37
-
156 (2)
(3)
37
-
41
-
41
-
37
-
Table 2–26. EP2S180 Differential Channels
Note (1)
Center Fast PLLs
Corner Fast PLLs (4)
Transmitter/
Receiver Channels
Total
Package
PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10
1,020-pin
FineLine BGA
Transmitter
Receiver
88 (2)
(3)
22
44
23
46
37
78
37
78
22
44
23
46
41
78
41
78
22
44
23
46
41
78
41
78
22
44
23
46
37
78
37
78
22
-
22
-
22
-
22
-
92 (2)
(3)
23
-
23
-
23
-
23
-
1,508-pin
FineLine BGA
Transmitter
Receiver
156 (2)
(3)
37
-
41
-
41
-
37
-
156 (2)
(3)
37
-
41
-
41
-
37
-
Notes to Tables 2–21 to 2–26:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
(2) This is the maximum number of channels the PLLs can directly drive.
(3) This is the maximum number of channels if the device uses cross bank channels from the adjacent center PLL.
(4) The channels accessible by the center fast PLL overlap with the channels accessible by the corner fast PLL.
Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number of channels accessible by PLLs 7, 8, 9, and 10.
Altera Corporation
May 2007
2–99
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
