Stratix II Architecture
Table 2–17. On-Chip Termination Support by I/O Banks (Part 2 of 2)
On-Chip Termination Support
I/O Standard Support
Top & Bottom Banks
Left & Right Banks
Series termination with
calibration
3.3-V LVTTL
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 Class I and II
SSTL-18 Class I and II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.2-V HSTL
Parallel termination with
calibration
SSTL-2 Class I and II
SSTL-18 Class I and II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I and II
1.2-V HSTL
LVDS
Differential termination (1)
v
v
HyperTransport technology
Note to Table 2–17:
(1) Clock pins CLK1, CLK3, CLK9, CLK11, and pins FPLL[7..10]CLKdo not support differential on-chip
termination. Clock pins CLK0, CLK2, CLK8, and CLK10do support differential on-chip termination. Clock pins in
the top and bottom banks (CLK[4..7, 12..15]) do not support differential on-chip termination.
Altera Corporation
May 2007
2–91
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
