AV-51002
2017.02.10
1-70
NAND Timing Characteristics
Figure 1-16: I2C Timing Diagram
I2C_SCL
Td
Ts
Tsu_stop
Tsu_start Thd_start
Th
Data Out
Data In
I2C_SDA
NAND Timing Characteristics
Table 1-60: NAND ONFI 1.0 Timing Requirements for Arria V Devices
e NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5 timing as well as legacy NAND devices. is table lists the
requirements for ONFI 1.0 mode 5 timing. e HPS NAND controller can meet this timing by programming the C4output of the main HPS PLL
and timing registers provided in the NAND controller.
Symbol
Description
Min
10
7
Max
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(89)
Twp
Twh
Write enable pulse width
Write enable hold time
Read enable pulse width
Read enable hold time
(89)
(89)
Trp
10
7
(89)
Treh
(89)
(89)
(89)
Tclesu
Command latch enable to write enable setup time
Command latch enable to write enable hold time
Chip enable to write enable setup time
10
5
(89)
Tcleh
Tcesu
15
5
(89)
Tceh
Talesu
Chip enable to write enable hold time
Address latch enable to write enable setup time
Address latch enable to write enable hold time
Data to write enable setup time
10
5
(89)
Taleh
(89)
Tdsu
10
(89)
Timing of the NAND interface is controlled through the NAND configuration registers.
Arria V GX, GT, SX, and ST Device Datasheet
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