AV-51002
2017.02.10
1-65
SD/MMC Timing Characteristics
Afer the Boot ROM code exits and control is passed to the preloader, sofꢂare can adjust the value of drvseland smplselvia the system manager.
drvselcan be set from 1 to 7 and smplselcan be set from 0 to 7. While the preloader is executing, the values for SDMMC_CLKand SDMMC_CLK_OUT
increase to a maximum of 200 MHz and 50 MHz respectively.
e SD/MMC interface calibration support will be available in a future release of the preloader through the SoC EDS sofꢂare update.
Symbol
Description
Min
Max
Unit
SDMMC_CLK clock period
20
—
ns
(Identification mode)
Tsdmmc_clk (internal reference
clock)
SDMMC_CLK clock period
(Default speed mode)
5
5
—
—
—
—
—
55
ns
ns
ns
ns
ns
SDMMC_CLK clock period
(High speed mode)
SDMMC_CLK_OUT clock
2500
40
period (Identification mode)
Tsdmmc_clk_out (interface output
clock)
SDMMC_CLK_OUT clock
period (Default speed mode)
SDMMC_CLK_OUT clock
period (High speed mode)
20
Tdutycycle
Td
SDMMC_CLK_OUT duty cycle
45
%
SDMMC_CMD/SDMMC_D
output delay
(Tsdmmc_clk × drvsel)/2 (Tsdmmc_clk × drvsel)/2
ns
– 1.23 (87)
+ 1.69 (87)
—
Tsu
Th
Input setup time
1.05 – (Tsdmmc_clk
×
ns
ns
smplsel)/2 (88)
Input hold time
(Tsdmmc_clk × smplsel)/
—
2 (88)
(87)
drvselis the drive clock phase shif select value.
smplselis the sample clock phase shif select value.
(88)
Arria V GX, GT, SX, and ST Device Datasheet
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