AV-51002
2017.02.10
1-63
SPI Timing Characteristics
Figure 1-9: SPI Master Timing Diagram
Tdsslst
SPI_SS
Tdssfrst
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Tdio
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
Th
Tsu
Tdio
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Th
Tsu
Table 1-53: SPI Slave Timing Requirements for Arria V Devices
e setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol
Description
Min
20
5
Max
—
—
—
—
—
6
Unit
ns
Tclk
Ts
CLK clock period
MOSI Setup time
MOSI Hold time
ns
Th
5
ns
Tsuss
Thss
Td
Setup time SPI_SS valid before first clock edge
Hold time SPI_SS valid afer last clock edge
MISO output delay
8
ns
8
ns
—
ns
Arria V GX, GT, SX, and ST Device Datasheet
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