AV-51002
2017.02.10
1-64
SD/MMC Timing Characteristics
Figure 1-10: SPI Slave Timing Diagram
Thss
SPI_SS
Tsuss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Td
SPI_MISO (scph = 1)
SPI_MOSI (scph = 1)
Ts
Th
Td
SPI_MISO (scph = 0)
Ts
Th
SPI_MOSI (scph = 0)
Related Information
SPI Controller, Arria V Hard Processor System Technical Reference Manual
Provides more information about rx_sample_delay.
SD/MMC Timing Characteristics
Table 1-54: Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria V Devices
Afer power up or cold reset, the Boot ROM uses drvsel= 3 and smplsel= 0 to execute the code. At the same time, the SD/MMC controller enters
the Identification Phase followed by the Data Phase. During this time, the value of interface output clock SDMMC_CLK_OUTchanges from a maximum
of 400 kHz (Identification Phase) up to a maximum of 12.5 MHz (Data Phase), depending on the internal reference clock SDMMC_CLKand the CSEL
setting. e value of SDMMC_CLKis based on the external oscillator frequency and has a maximum value of 50 MHz.
Arria V GX, GT, SX, and ST Device Datasheet
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