AV-51002
2017.02.10
1-62
SPI Timing Characteristics
Symbol
Description
Min
1
Max
—
55
—
—
1
Unit
ns
Th
SPI MISO hold time
SPI_CLK duty cycle
Tdutycycle
Tdssfrst
Tdsslst
Tdio
45
8
%
Output delay SPI_SS valid before first clock edge
Output delay SPI_SS valid afer last clock edge
Master-out slave-in (MOSI) output delay
ns
8
ns
–1
ns
(86)
is value is based on rx_sample_dly= 1 and spi_m_clk= 120 MHz. spi_m_clkis the internal clock that is used by SPI Master to derive it’s SCLK_
OUT. ese timings are based on rx_sample_dlyof 1. is delay can be adjusted as needed to accommodate slower response times from the slave.
Note that a delay of 0 is not allowed. e setup time can be used as a reference starting point. It is very crucial to do a calibration to get the correct rx_
sample_dlyvalue because each SPI slave device may have different output delay and each application board may have different path delay. For more
information about rx_sample_delay, refer to the SPI Controller chapter in the Hard Processor System Technical Reference Manual.
Arria V GX, GT, SX, and ST Device Datasheet
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