欢迎访问ic37.com |
会员登录 免费注册
发布采购

5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第68页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第69页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第70页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第71页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第73页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第74页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第75页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第76页  
AV-51002  
2017.02.10  
I2C Timing Characteristics  
1-69  
Figure 1-15: MDIO Timing Diagram  
MDC  
Td  
MDIO_OUT  
Th  
Tsu  
MDIO_IN  
I2C Timing Characteristics  
Table 1-59: I2C Timing Requirements for Arria V Devices  
Standard Mode  
Fast Mode  
Symbol  
Description  
Unit  
Max  
Min  
Max  
Min  
2.5  
0.6  
1.3  
0.1  
0
Tclk  
Serial clock (SCL) clock period  
SCL high time  
10  
4.7  
4
0.9  
0.2  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
Tclkhigh  
Tclklow  
Ts  
SCL low time  
Setup time for serial data line (SDA) data to SCL  
Hold time for SCL to SDA data  
0.25  
0
Th  
3.45  
0.2  
Td  
SCL to SDA output data delay  
4.7  
4
Tsu_start  
Thd_start  
Tsu_stop  
Setup time for a repeated start condition  
Hold time for a repeated start condition  
Setup time for a stop condition  
0.6  
0.6  
0.6  
4
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
 复制成功!