AV-51002
2017.02.10
1-61
SPI Timing Characteristics
Symbol
Description
Min
Typ
Max
Unit
Tdin_end
Input data valid end
(2 + Rdelay) ×
—
—
ns
Tqspi_clk – 1.21 (85)
Figure 1-8: Quad SPI Flash Timing Diagram
is timing diagram illustrates clock polarity mode 0 and clock phase mode 0.
Tdsslst
QSPI_SS
SCLK_OUT
QSPI_DATA
Tdssfrst
Tdio
Tdin_start
Data Out
Data In
Tdin_end
Related Information
Quad SPI Flash Controller Chapter, Arria V Hard Processor System Technical Reference Manual
Provides more information about Rdelay.
SPI Timing Characteristics
Table 1-52: SPI Master Timing Requirements for Arria V Devices
e setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol
Description
Min
Max
Unit
ns
Tclk
Tsu
CLK clock period
SPI Master-in slave-out (MISO) setup time
16.67
8.35 (86)
—
—
ns
(85)
Rdelay is set by programming the register qspiregs.rddatacap. For the SoC EDS sofꢂare version 13.1 and later, Altera provides automatic Quad SPI
calibration in the preloader. For more information about Rdelay, refer to the Quad SPI Flash Controller chapter in the Arria V Hard Processor System
Technical Reference Manual.
Arria V GX, GT, SX, and ST Device Datasheet
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