AV-51002
2017.02.10
2-42
Memory Block Specifications
Performance
Mode
Unit
C3, I3L
380
C4
I4
One sum of two 27 × 27
One sum of two 36 × 18
One complex 18 × 18
300
290
MHz
MHz
MHz
MHz
380
300
350
300
400
One 36 × 36
380
Modes using ree DSP Blocks
One complex 18 × 25
340
350
275
265
MHz
MHz
Modes using Four DSP Blocks
One complex 27 × 27
310
Memory Block Specifications
Table 2-36: Memory Block Performance Specifications for Arria V GZ Devices
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set
to 50% output duty cycle. Use the Quartus II sofꢂare to report timing for this and other memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in FMAX
.
Resources Used
ALUTs Memory
Performance
Memory
Mode
Unit
C3
C4
I3L
400
400
533
500
I4
Single port, all supported widths
Simple dual-port, x32/x64 depth
Simple dual-port, x16 depth (178)
ROM, all supported widths
0
0
0
0
1
1
1
1
400
400
533
500
315
315
400
450
315
315
400
450
MHz
MHz
MHz
MHz
MLAB
(178)
e FMAX specification is only achievable with Fitter options, MLAB Implementation In 16-Bit Deep Mode enabled.
Arria V GZ Device Datasheet
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