AV-51002
2017.02.10
2-39
PLL Specifications
Symbol
Parameter
Min
—
Typ
—
Max
0.15
+750
175
Unit
Input clock cycle-to-cycle jitter (fREF ≥ 100 MHz)
Input clock cycle-to-cycle jitter (fREF < 100 MHz)
UI (p-p)
ps (p-p)
ps (p-p)
(171) (172)
tINCCJ
,
-750
—
—
Period Jitter for dedicated clock output in integer
PLL (fOUT ≥ 100 MHz)
—
(173)
tOUTPJ_DC
tFOUTPJ_DC
tOUTCCJ_DC
Period Jitter for dedicated clock output in integer
PLL (fOUT < 100 Mhz)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17.5
mUI (p-p)
ps (p-p)
Period Jitter for dedicated clock output in fractional
PLL (fOUT ≥ 100 MHz)
250(176)
,
175(174)
(173)
(173)
Period Jitter for dedicated clock output in fractional
PLL (fOUT < 100 MHz)
25(176)
,
mUI (p-p)
ps (p-p)
17.5 (174)
175
Cycle-to-cycle Jitter for a dedicated clock output in
integer PLL (fOUT ≥ 100 MHz)
Cycle-to-cycle Jitter for a dedicated clock output in
integer PLL (fOUT < 100 MHz)
17.5
mUI (p-p)
ps (p-p)
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT ≥ 100 MHz)
250(176)
175 (174)
,
(173)
tFOUTCCJ_DC
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT < 100 MHz)
25(176)
,
mUI (p-p)
17.5 (174)
(171)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
e fREF is fIN/N specification applies when N = 1.
(172)
(173)
Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence levelꢁ.)e output jitter specification applies to the
intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. e external memory interface clock output jitter specifications use a different
measurement method and are available in the "Worst-Case DCD on Arria V GZ I/O Pins" table.
(174)
is specification only covered fractional PLL for low bandwidth. e fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
Arria V GZ Device Datasheet
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