AV-51002
2017.02.10
2-40
PLL Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Period Jitter for a clock output on a regular I/O in
integer PLL (fOUT ≥ 100 MHz)
—
—
600
ps (p-p)
, (173) (175)
tOUTPJ_IO
,
Period Jitter for a clock output on a regular I/O in
integer PLL (fOUT < 100 MHz)
—
—
—
—
—
—
—
—
—
8
—
—
—
—
—
—
—
—
—
24
60
600
60
mUI (p-p)
ps (p-p)
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT ≥ 100 MHz)
(173) (175) (176)
tFOUTPJ_IO
tOUTCCJ_IO
tFOUTCCJ_IO
,
,
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular
I/O in integer PLL (fOUT ≥ 100 MHz)
600
60
(173) (175)
,
Cycle-to-cycle Jitter for a clock output on a regular
I/O in integer PLL (fOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular
I/O in fractional PLL (fOUT ≥ 100 MHz)
600
60
(173) (175) (176)
,
,
Cycle-to-cycle Jitter for a clock output on a regular
I/O in fractional PLL (fOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Period Jitter for a dedicated clock output in
cascaded PLLs (fOUT ≥ 100 MHz)
175
17.5
32
(173) (177)
tCASC_OUTPJ_DC
,
Period Jitter for a dedicated clock output in
cascaded PLLS (fOUT < 100 MHz)
mUI (p-p)
Bits
dKBIT
Bit number of Delta Sigma Modulator (DSM)
(175)
e external memory interface clock output jitter specifications use a different measurement method, which is available in the "Memory Output Clock
Jitter Specification for Arria V GZ Devices" table.
(176)
(177)
is specification only covered fractional PLL for low bandwidth. e fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
e cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59Mhz ≤ Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
Arria V GZ Device Datasheet
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