AV-51002
2017.02.10
2-38
PLL Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Output frequency for an internal global or regional
clock (C3, I3L speed grade)
—
—
650
MHz
(169)
fOUT
Output frequency for an internal global or regional
clock (C4, I4 speed grade)
—
—
—
45
—
—
—
50
580
667
533
55
MHz
MHz
MHz
%
Output frequency for an external clock output (C3,
I3L speed grade)
(169)
fOUT_EXT
Output frequency for an external clock output (C4,
I4 speed grade)
tOUTDUTY
Duty cycle for a dedicated external clock output
(when set to 50%)
tFCOMP
External feedback clock compensation time
—
—
—
—
10
ns
fDYCONFIGCLK
Dynamic configuration clock for mgmt_clkand
scanclk
100
MHz
tLOCK
Time required to lock from the end-of-device
—
—
—
—
1
1
ms
ms
configuration or deassertion of areset
tDLOCK
Time required to lock dynamically (afer switchover
or reconfiguring any non-post-scale counters/
delays)
PLL closed-loop low bandwidth
—
—
—
—
10
0.3
1.5
4
—
—
—
50
—
MHz
MHz
MHz
ps
fCLBW
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth (170)
Accuracy of PLL phase shif
tPLL_PSERR
tARESET
—
—
Minimum pulse width on the aresetsignal
ns
(169)
is specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
High bandwidth PLL settings are not supported in external feedback mode.
(170)
Arria V GZ Device Datasheet
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