Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Date
Version
Changes
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Updated TCCS specifications in the following tables:
— True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
Updated tx Jitter specifications in the following tables:
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— True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
Updated SW specifications in LVDS Receiver Timing Specifications for Intel MAX 10 Single Supply Devices table.
Added a note to tx Jitter for all LVDS tables. Note: TX jitter is the jitter induced from core noise and I/O switching noise.
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Updated the description for tLOCK for all LVDS tables: Time required for the PLL to lock, after CONF_DONE signal goes high,
indicating the completion of device configuration.
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Updated Memory Output Clock Jitter Specifications section.
— Updated maximum external memory interfaces frequency from 300 MHz to 303 MHz.
— Updated PLL output routing from global clock network to PHY clock network.
Added I/O Timing for Intel MAX 10 Devices table.
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Added VHYS in the Glossary table.
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Intel® MAX® 10 FPGA Device Datasheet
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